1. Field of the Invention
The present invention relates to data transmitting and receiving interface devices and, more particularly, to a combined hardware and software interface that substantially increases the speed of data transmission and reception between a variety of communication devices.
2. Description of Related Art
With the increase in the development of computer and telephone communications systems requiring expanded data conversion and processing capabilities, there is a continuing need to minimize error and data loss between data terminal equipment (DTE) and data communication equipment (DCE). For example, the increased use of audio technology requires high speed voice data processing capabilities at very high sampling rates. Such advanced technologies, in turn, require extremely fast data throughput processing for transmitting and receiving voice data through the DCE. Increased processing, however, tends to produce the aforementioned undesirable data errors and losses.
A conventional DCE implementation generally includes a modem (modulator/demodulator) coupled to the DTE. The DTE typically includes an arrangement of a personal computer (PC) having a central processing unit (CPU) and additional processing devices which may be internal or external to the base computer. The PC CPU typically drives all or most of the operating functions of the PC. To communicate with other data processing devices, the PC may be coupled to the DCE, e.g., the modem peripheral, by a serial or parallel data bus.
A conventional modem peripheral may include a standard universal asynchronous receiver/transmitter (UART) or UART emulator in which the format of incoming data is converted. A UART device is necessary to achieve compatibility between a standard PC and a serial peripheral device, such as a modem. A UART essentially functions as a serial-to-parallel or parallel-to-serial converter, depending upon whether the modem is in a receive or transmit mode, respectively. As shown in FIG. 5, within the modem peripheral device 500, a UART 501 is coupled to a modem controller 502 which has another UART 504 embedded therein. Parallel data signals may be directed across a DTE/DCE interface bus 514 via an application program 516 coupled to the standard PC (not shown). The data signals are processed by the UART 501 and converted to serial format. The serial data 508 output from the first UART 501 is converted by the modem controller 502 to parallel data, and is processed and manipulated through one or more memory devices 512. The modem controller 502 includes embedded firmware 520 held in a ROM for controlling the operation of the controller 502. For example, the firmware 520 may be used to pass data, accept data, and other similar functions for which it may be prohibitive to except discrete hardware to perform. Typically, the embedded firmware is considered part of the controller hardware. Ultimately, the data is passed through a data pump 506, and output over the public switched telephone network (PSTN) 510 or other output device, such as a speaker in the case of audio data. Likewise, data from the PSTN or microphone is converted to serial by the modem controller UART 504 and converted to parallel by the PC UART 501, and directed to the PC application program 516.
Referring to FIG. 5, the primary function of the modem 500 is to allow the transmission and reception of data over a telephone medium 510, e.g., via established telephone lines. In addition, other voice modes may be used in which a phone line is not required. For example, analog voice signals may be passed to or from other hardware, such as speakers or microphones directly, without the involvement of a telephone line. In any case, transmitted and received signals comprise analog waveforms which are modulated and demodulated to create and interpret the signals that carry data or voice over the telephone lines or other hardware interfaces.
More particularly, a standard UART in a modem device typically processes data by receiving a "block" of data from either the DTE (during a transmit operation) or a remote DCE (during a receive operation). Upon processing and, thus, converting the data format, the UART outputs the data to the DCE or the DTE during a transmit or receive operation, respectively. After each data output activity performed by the UART, the modem controller causes an interrupt request to be sent to the DTE to request transmission or reception of another block of data. In some instances, the PC may use polling to continuously inquire if data should be read or written.
For example, a 1-byte deep UART operates by transmitting or receiving 1 byte of data in response to each interrupt request. During a transmit operation, for example, as data is transmitted from the CPU to the UART, it is first processed through a holding register before being moved into a shift register. As the data leaves the UART holding register, the holding register becomes empty. Upon detection of the empty condition by the modem controller, an interrupt request is sent to the CPU requesting another byte of data. The above-described sequence is then repeated. Another type of conventional UART includes a 16-byte deep holding register which enables the transfer of up to 16 bytes of data at one time before the CPU is interrupted for service (i.e., to transmit or receive an additional block of data). Thus, the CPU may maintain up to 16 character times worth of data in the holding register before responding to another interrupt request from the UART.
UART emulation (see generally FIG. 6) effectively presents itself in UART format 600 by utilizing a timer and predesignated data registers 602 to emulate the UART function. It will be recognized, however, that but for the sake of compatibility with the DTE software, there is no need to actually serialize data. In standard UART emulators, a clock timer inserts standard-length data transfer delays which would otherwise be representative of a conventional UART. However, because UART emulators are, by definition, designed only to mimic the data processing functions of a standard UART, the data processing rates are accordingly limited.
Although conventional UARTs may be adequate for a variety of computer applications, it has been found that some input/output (I/O)-intensive computer processes require even greater throughput and performance than that available using standard serial I/O interfaces due to ever-increasing modulation speeds and increased functions such as voice and audio transmission. Depending upon the particular application software being used, the PC may not have sufficient time to service all of the processing interruptions. The time constraints are often attributable to competing interrupt sources and/or latency effects introduced by other interrupt mechanisms which are inherent in the DTE hardware and/or the operating system. Accordingly, insufficient PC time and effort may be available for driving and supporting a high data rate in addition to the data processing requirements of other software applications which may be concurrently running, thus resulting in losses of data.
For example, a communication application generally includes what may be considered foreground and background tasks (these terms may be reversed). The foreground may comprise multiple specially-installed programs which operate at a predetermined rate, while the background include tasks which must occur promptly upon receiving a particular signal such as an interrupt. In this example, data may be moved from or to the DCE by the background, and then moved to the DTE by the foreground. However, if the background is slow and requires excessive time to complete its functions, and thus cannot service the DCE sufficiently promptly, or if the background leaves insufficient time for the communication application foreground to keep up with the background data flow, data overruns and underruns could occur.
It is believed that one cause of undesirable delays in PC response times is attributable to the amount of time spent on servicing the sometimes large number of interrupt request. For example, in a computer system in which the data exchange/transmission rate between the DTE and the modem is 9600 bits per second (bps), the pulsewidth of each bit time is approximately equal to 100 microseconds. Thus, the time necessary to output one data bit is approximately 100 microseconds. However, if the CPU sends 1 byte (8 bits) of data, the actual number of bits typically includes one start bit and one stop bit in addition to the 8 data bits, totaling 10 bits. Accordingly, each byte of data transmitted at 9600 bps between the host CPU and the modem peripheral requires approximately 1 millisecond of time (10 data bits multiplied by 100 microseconds per bit).
Furthermore, because in some UARTs each interrupt request comprises one byte of data (e.g., in a 1-byte deep UART), each interrupt request sent to the DTE by the modem controller is periodically set at 1 millisecond intervals. As a result, approximately two milliseconds of CPU processing time could be required to respond to each interrupt request. If a large amount of data is to be transmitted or received, the amount of CPU processing time expended on servicing the interrupt could become significant. More particularly, because a large number of interrupts may occur requiring long interrupt service times, the DTE time spent for interrupt service may exceed the period of the interrupt. Data may also be lost if the DTE spends additional time which exceeds the period of the interrupt in other interrupt services or system-critical tasks which may occur at unpredictable times and rates, beyond the control of the interrupt routine.
Another time-limiting disadvantage attributable to the DTE response time necessary to service pending conditions is called latency. Latency refers to the time necessary for the DTE to notice and begin to service an interrupt request. Latency also refers to the time necessary for the modem to notice that the transmit register contains data or that the receive register is empty. Undesirable latency periods may occur when the DTE is too busy to service data before it is lost or if the PC is waiting to send or receive data while it services the interrupts. The length and occurrence of latency periods are generally random and often depend upon other processing being performed by the operating system at any time. Such processes may include preparing data for transmission and storing received data.
Thus, it is desirable to maximize the data transfer rate between the DTE and the DCE, yet also to minimize the number of PC interrupts and the accompanying interrupt overhead. Accordingly, it is also desirable to expend DTE processing time to drive certain operating tasks while simultaneously maintaining its modem processing responsibilities, such as servicing interrupt requests. For example, a PC must often maintain the ability to receive data such is fax, voice message or other uploaded files, while concurrently performing a variety of other tasks such as compilation, printing, or word processing.
In particular, with respect to I/O-intensive Microsoft windows application, it has been found that data processing errors may occur when a modem peripheral device is used simultaneously with other windows environment. Because a substantial amount of CPU time and effort are directed to operating the windows application and since the CPU may be visibly servicing other foreground and background operations, the DTE may be unable to immediately service the UART interrupts. Thus, increased data processing and communications throughput rates have been sought to address the requirements of new and existing applications programs which require significantly higher data transfer rates.